Logic/Verification Design Engineer
- Experience Range: At least 3 YOE
- Job Location: Hanoi & HCMC
- Duty & Responsibilities:
• To be responsible for managing technology in projects and providing technical guidance or
solutions for work completion
• To be responsible for providing technical guidance or solutions
• To develop and guide the team members in enhancing their technical capabilities and increasing
• To prepare and submit status reports for minimizing exposure and risks on the project or closure
• To ensure process compliance in the assigned module, and participate in technical discussions or
• 3-10 years of Experience.
• Experience on logic design, lint check, synthesis, equivalence check, CDC verification.
• Experience on logic verification, System Verilog, UVM, Code Coverage, Assertions.
• Experience on chip level verification, ARM cores, Protocols ( PCIe, Ethernet, USB, DDR etc….
• Experience on following tools: Design Compiler, Formality, Conformal, Spyglass.
• Good command of English. Have chance to work onsite in Japan.
• 18 paid leaves per year (including 12 annual leaves + 6 personal leaves).
• Insurance plan based on full salary + 13th salary + Performance Bonus.
• 100% full salary in probation period.
• Medical Benefit (Personal) and Family based on levels.
• Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
• Internal Training (Technical & Functional). Scope of English Training.
• Working time: 8:30 am-6:00 pm from Mondays to Fridays.
- Preferred Language for Application: English