– Synthesis, P&R, and timing closure of various design IPs into FPGAs
– Functional and timing verification of FPGA design using simulation
– In-system verification of FPGA design on the system
– Writing verification test benches and automation of test cases
– Regression testing of FPGAs (simulation and in-system)
– Verification of serdes, BER testing and eye diagram verification

– Strong digital design concepts
– Good understanding of FPGA architecture of leading vendors is must
– Experience in Static timing analysis, timing constrains, clock-domain crossing is must
– Hands-on experience with EDA tools on timing closure is must
– Experience in verification/simulation tools is must
– Knowledge of scripting languages Perl, Python, TCL is preferred
– Knowledge of version control systems like svn/cvs is preferred
– Experience with FPGA test automation / regression is preferred
– Good documentation and communication skills
– Ability to guide /mentor junior members of team
– Understanding of OTN/Ethernet and 5G communication technologies are a plus

– 18 paid leaves per year (including 12 annual leaves + 6 personal leaves).
– Insurance plan based on full salary + 13th salary + Performance Bonus.
– 100% full salary in probation period.
– Medical Benefit (Personal) and Family based on levels.
– Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
– Internal Training (Technical & Functional). Scope of English Training.
– Working time: 8:30 am-6:00 pm from Mondays to Fridays.